1. Field of the Invention
The present invention relates to a memory device that makes a byte-unit access to a DRAM, particularly to a wide-bus DRAM core stored in a system LSI.
2. Description of the Related Art
First of all, the background of the present invention is briefly explained.
Due to the recent drastic fall of the price of general-purpose memories, people have more expectation for system LSIs, above all for those provided with a DRAM having a vast capacity and logic elements in a hybrid manner, as they are capable of implementing an improvement of transmission rate between the DRAM and logic elements, and a reduction of power consumption by storing a wide-bus DRAM of 128 bits and/or 256 bits therein, which are additional values that the general-purpose DRAMS are not provided with.
However, as the bus width provided by the general purpose DRAMs is usually as wide as 32 bits at most, users of the conventional general purpose DRAMs have been demanding DRAM cores of 32-bit or 64-bit narrow width. This requirement of the users has been compensated by carrying out a byte-unit access in which the wide-bus DRAM is controlled by many /CAS (column address strobe) signals.
FIG. 18 is a schematic diagram showing the configuration of a conventional memory device (a 128-bit DRAM core). In the figure, each reference numeral 1 denotes a byte-unit memory block storing therein memory cells configuring the DRAM core, reference numeral 2 denotes a column decoder for decoding a column address, numeral 3 denotes a memory cell storing therein a sense amplifier, 4 denotes a one-byte preamplifier that reads one-byte data from the memory cell 3 and amplifies the signal level of the thus read data, and numeral 5 denotes a one-byte output buffer that temporally holds the one-byte data output from the preamplifier 4 and externally outputs the thus held data.
Further, reference numeral 6 denotes a one-byte input buffer that inputs data to be stored in the memory cell 3 and temporally stores the thus input data, numeral 7 denotes a one-byte write buffer for writing the data fed from the input buffer 6 into the memory cell 3, numeral 8 denotes a CAS buffer that inputs a /CAS&lt;i&gt; signal (i=0.about.15 throughout the specification) and outputs a control signal for controlling the output buffer 5 and so on, numerals 9 and 10 denote logic elements, 11 denotes an AND circuit for performing ANDing operation of /CASFF&lt;i&gt; signals output from the CAS buffer 8 of each of the memory blocks, 12 denotes a clock generator, 13-15 denote logic elements, 16 denotes a column address buffer for storing a column address, 17 denotes a row address buffer for storing a row address, and numeral 18 denotes a row decoder for decoding the row address.
FIG. 19 is a schematic diagram showing the detailed inner configuration of the memory block 1. In this figure, reference numeral 1a denotes a one-bit memory block, numeral 2a denotes a one-bit column decoder, 3a denotes a memory cell that allows an access of bit-unit data, 4a denotes a one-bit preamplifier, 5a denotes a one-bit output buffer, 6a denotes a one-bit input buffer, and numeral 7a denotes a one-bit write buffer.
It is to be noted that when the CAS buffer 8 inputs a /CAS&lt;i&gt; signal of L level (hereinafter may be referred to as "L" level or just "L"), input or output of one-byte data is enabled, and a /CASFF&lt;i&gt; signal output from the CAS buffer 8 is ANDed by an AND circuit 11 with other /CASFF&lt;i&gt; signals, so as to generate a /CASM signal that controls the entire DRAM.
Further, a /CASF&lt;i&gt; signal output from the CAS buffer 8 generates a WBE&lt;i&gt; signal for controlling the one-byte write buffer 7, in cooperation with a WBEM signal which is common to all bytes, whereas a /CASD&lt;i&gt; signal, which is also output from the CAS buffer 8, generates an OE&lt;i&gt; signal for controlling the one-byte output buffer 5, in cooperation with an OEM signal which is common to all bytes.
Further, a CDEM signal, a PAEM signal and a DILM signal, respectively controlling the column decoder 2, the preamplifier 4 and the input buffer 6, and an ODLM signal for writing data from a latch circuit (hereinafter referred to just as a "latch") in the preamplifier 4 to that of the output buffer 5 are all common to all bytes.
The block shown in the left side of FIG. 20 is a decoder circuit for generating a plurality of /CAS&lt;i&gt; signals and outputting these signals to a 128-byte DRAM core, wherein the decoder circuit 20 inputs an ABS signal capable of simultaneously selecting all bytes, and generates CAS&lt;0&gt; to CAS&lt;15&gt; signals (hereinafter CAS&lt;0.about.15&gt;) for specifying each byte in combination with address signals A&lt;0&gt; to A&lt;3&gt; (abbreviated hereinafter to A&lt;0.about.3&gt;) and a main /CAS signal.
When executing a byte-unit accessing operation, in the case that the ABS signal is in the "L" level, the address signals A&lt;0.about.3&gt; can be regarded as corresponding to column address CA&lt;5.about.8&gt; which are upper than the column address CA&lt;0.about.4&gt; of the DRAM.
FIG. 21 is a diagram showing the data corresponding to each of the CAS&lt;i&gt; signals and the assignment of the address signals A&lt;0.about.3&gt; to the column address CA&lt;5.about.8&gt; at the time of the above byte-unit accessing operation.
The operation of the conventional memory device is now explained below.
The explanation is given with reference to FIGS. 22 and 23, on the assumption that the memory block 1 which is controlled by the /CAS&lt;1&gt; signal is a non-selected byte, and the memory block 1 which is controlled by the /CAS&lt;2&gt; signal is a selected byte.
In the data reading mode as shown in FIG. 22, each of the CDEM signal and the PAEM signal, which are common to all bytes, becomes a pulse signal of "H" level in accordance with the change of the column address after the fall of the /RAS (row address strobe) signal which is an external input of the DRAM core.
On this occasion, in both the selected and non-selected bytes, the column decoder 2 and the preamplifier 4 operate, whereby the latch of the preamplifier 4 reads out one-byte data (designated by the column address and the row address) from the memory cell 3 and stores therein.
In the selected byte, when the /CASM signal, that controls the entire DRAM, falls due to the fall of the /CAS&lt;2&gt; signal, the level of the CDEM signal and that of the PAEM signal are fixed to "L", and thereafter, when the level of the ODLM signal becomes "L", the data fed from the latch of the preamplifier 4 is written into the latch of the output buffer 5.
Thereafter, in the selected byte, when the level of the OE&lt;2&gt; signal is fixed to "H" due to the fact that the OEM signal becomes "H" level, the data is output externally from the latch of the output buffer 5.
On the other hand, in the non-selected byte, since the level of the /CAS&lt;1&gt; signal is held in the "H" level, the OE&lt;1&gt; signal is fixed to "L" level, so that no data is output from the latch of the output buffer 5.
In the data writing mode as shown in FIG. 23, the CDEM signal which is common to all bytes becomes a pulse signal of "H" level in accordance with the change of the column address after the fall of the /RAS signal which is an external input of the DRAM core. On this occasion, the column decoder 2 operates in both the selected and non-selected bytes.
In the selected byte, when the /CASM signal that controls the entire DRAM falls due to the fall of the /CAS&lt;2&gt; signal, the level of the CDEM signal becomes "L".
At the time of early writing, the DILM signal becomes a pulse signal of "L" level due to the fall of the /CASM signal, and the input buffer 6 inputs a data to be written from outside.
Thereafter, when the level of the WBEM signal which is a control signal common to all bytes becomes a pulse signal of "H" level, in the selected byte, the WBE&lt;2&gt; signal becomes a pulse signal of "H" level, and the data held in the latch of the input buffer 6 is written into the memory cell 3.
On the other hand, in the non-selected byte, sine the WBE&lt;1&gt; signal is still in the "L" level, the data held in the latch of the input buffer 6 is not written into the memory cell 3.
Note that in FIGS. 22 and 23, tASR and tRAH respectively denote a set-up time and a hold time of the row address of the DRAM, whereas tASC and tCAH denote respectively a set-up time and a hold time of the column address.
Since the conventional memory cell is configured as such, although the memory block 1, which receives a /CAS&lt;i&gt; signal whose signal level changes from "H" to "L" after the fall of the /RAS signal, becomes a selected byte, it cannot be decided as to whether the corresponding memory block 1 becomes a selected or a non-selected byte as long as the /CAS&lt;i&gt; signal does not fall.
Due to this, the column decoder 2 and the preamplifier 4, which start operating in accordance with the fall of the /RAS signal, cannot be controlled (in other words, even in the case where the corresponding memory block 1 becomes a non-selected byte, the column decoder 2 and the preamplifier 4 cannot be inactivated, and thus, they operate unnecessarily), and accordingly there has been such a problem that the overall power consumption cannot be reduced efficiently.